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Accelerated Computing: A Tipping Point for HPC

by Christopher G. Willard, Ph.D., Addison Snell, Michael Feldman
for Intersect360 Research
November 2015
 
EXECUTIVE SUMMARY

The High Performance Computing (HPC) industry has gone through several eras marked by distinct architectures, each with its own programming model for application scalability. For decades vector processing was dominant, with codes that were “vectorized” to take full advantage of the model. But soon scalar processors became more economically viable, and a generation of RISC-based symmetric multi-processing (SMP) architectures dominated the market, using shared-memory programming models such as OpenMP. In the late 1990s, x86-based clusters came into the market, following the “Beowulf” model of industry-standard parts into commodity HPC systems, and the application base migrated to message-passing parallelism techniques such as MPI.
 
Over the last three years, accelerators have become firmly established in high performance computing (HPC), a significant part of the transition into another new era of HPC, the many-core era. Like previous architectural transitions, this migration is being driven by the economics of price/performance. More cores yield more computational power. This newest transition is amplified by a supply-side shift, as the breakdown of Moore’s Law and Dennard scaling leaves the market no choice but to evolve.

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